LPC-E2468 development board
Users Manual
Rev.B, February 2008
Copyright(c) 2008, OLIMEX Ltd, All rights reserved
INTRODUCTION:
LPC-E2468 uC Linux development prototype board with LPC2468 USB,
Ethernet, SD/MMC in credit card format.
BOARD FEATURES:
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MCU:
LPC2468;
16MB SDRAM;
128 MB NAN Flash;
standard JTAG connector with ARM
programming/debugging with ARM-JTAG;
Ethernet 100MBit;
2x USB hosts;
USB-to-RS232 converter device connected to LPC2468 UART;
SD/MMC card connector;
UEXT connector with I2C, SPI, RS232 and power supply for
connecting add-on modules like RF link, MP3, etc available from
Olimex;
trimpot connected to ADC;
RESET circuit with external control of Philips ISP utility via RS232
port;
two USER button;
RESET Button;
two on board voltage regulators 3V and 5V with up to 800mA
current;
Extension port connector for many of microcontrollers pins;
single power supply: External power supply, USB or JTAG connector;
Battery holder and connector for the RTC;
power supply led;
FR-4, 1.5 mm, red soldermask, component print;
Dimensions: 90x60mm (3.54 x 2.36").
2x10
pin
layout
for
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ELECTROSTATIC WARNING:
The LPC-E2468 development board is shipped in protective anti-static
packaging. The board must not be subject to high electrostatic potentials.
General practice for working with static sensitive devices should be applied
when working with this board.
BOARD USE REQUIREMENTS:
Cables:
USB A-B cable to connect to virtual serial port on the board.
You will need LPT cable if you want to program the MCU with
AVR-JTAG. You might need other cables in case of other
programmers/debuggers.
Programmer/debugger AVR-JTAG or any compatible tool.
The board is delivered with uC Linux pre-loaded. You could
develop projects for the board with Eclipse, IAR, etc. Please,
refer to the
LPC-E2468 Quickstart Guide
which is on the CD
for more details on the software requirements.
Hardware:
Software:
PROCESSOR FEATURES:
The
LPC2468
processor has the following features:
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ARM7TDMI-S processor, running at up to 72 MHz.
512 kB on-chip flash program memory with In-System Programming
(ISP) and In-Application Programming (IAP) capabilities. Flash
program memory is on the ARM local bus for high performance CPU
access.
98 kB on-chip SRAM includes:
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64 kB of SRAM on the ARM local bus for high performance CPU
access.
16 kB SRAM for Ethernet interface. Can also be used as
general purpose SRAM.
16 kB SRAM for general purpose DMA use also accessible by
the USB.
2 kB SRAM data storage powered from the Real-Time Clock
(RTC) power domain.
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Dual Advanced High-performance Bus (AHB) system allows
simultaneous Ethernet DMA, USB DMA, and program execution
from on-chip flash with no contention.
EMC provides support for asynchronous static memory devices such
as RAM, ROM and flash, as well as dynamic memories such as
Single Data Rate SDRAM.
Advanced Vectored Interrupt Controller (VIC), supporting up to 32
vectored interrupts.
General Purpose AHB DMA controller (GPDMA) that can be used
with the SSP,
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S-bus, and SD/MMC interface as well as for memory-to-memory
transfers.
Serial Interfaces:
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Ethernet MAC with MII/RMII interface and associated DMA
controller. These functions reside on an independent AHB bus.
USB 2.0 full-speed dual port Device/Host/OTG Controller with
on-chip PHY and associated DMA controller.
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Four UARTs with fractional baud rate generation, one with
modem control I/O, one with IrDA support, all with FIFO.
CAN controller with two channels.
SPI controller.
Two SSP controllers, with FIFO and multi-protocol capabilities.
One is an alternate for the SPI port, sharing its interrupt. SSPs
can be used with the GPDMA controller.
Three I
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C-bus interfaces (one with open-drain and two with
standard port pins).
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S (Inter-IC Sound) interface for digital audio input or output.
It can be used with the GPDMA.
SD/MMC memory card interface.
160 General purpose I/O pins with configurable pull-up/down
resistors.
10-bit ADC with input multiplexing among 8 pins.
10-bit DAC.
Four general purpose timers/counters with 8 capture inputs
and 10 compare outputs. Each timer block has an external
count input.
Two PWM/timer blocks with support for three-phase motor
control. Each PWM has an external count inputs.
RTC with separate power domain, clock source can be the RTC
oscillator or the APB clock.
2 kB SRAM powered from the RTC power pin, allowing data to
be stored when the rest of the chip is powered off.
WatchDog Timer (WDT). The WDT can be clocked from the
internal RC oscillator, the RTC oscillator, or the APB clock.
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Other peripherals:
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Standard ARM test/debug interface for compatibility with existing
tools.
Emulation trace module supports real-time trace.
Single 3.3 V power supply (3.0 V to 3.6 V).
Three reduced power modes: idle, sleep, and power-down.
Four external interrupt inputs configurable as edge/level sensitive.
All pins on PORT0 and PORT2 can be used as edge sensitive
interrupt sources.
Processor wake-up from Power-down mode via any interrupt able to
operate during Power-down mode (includes external interrupts, RTC
interrupt, USB activity, Ethernet wake-up interrupt, CAN bus
activity, PORT0/2 pin interrupt).
Two independent power domains allow fine tuning of power
consumption based on needed features.
Each peripheral has its own clock divider for further power saving.
These dividers help reducing active power by 20 - 30 %.
Brownout detect with separate thresholds for interrupt and forced
reset.
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On-chip power-on reset.
4 MHz internal RC oscillator trimmed to 1 % accuracy that can
optionally be used as the system clock. When used as the CPU clock,
does not allow CAN and USB to run.
On-chip PLL allows CPU operation up to the maximum CPU rate
without the need for a high frequency crystal. May be run from the
main oscillator, the internal RC oscillator, or the RTC oscillator.
Boundary scan for simplified board testing.
Versatile pin function selections allow more possibilities for using
on-chip peripheral functions.
On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
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